1. Field of the Invention
The present invention generally relates to the fabrication and design of semiconductor chips and integrated circuits, specifically to a method of modeling the operation of a circuit running under asynchronous conditions, and more particularly to a model transformation for clock-gated logic that may be implemented as free-running, data-gated logic.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements grouped to perform a logic function. Cell types include, for example, core cells, scan cells and input/output (I/O) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip. For more complex designs, there are typically at least four distinct layers of conducting media available for routing, such as a polysilicon layer and three metal layers (metal-1, metal-2, and metal-3). The polysilicon layer, metal-1, metal-2, and metal-3 are all used for vertical and/or horizontal routing.
An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a “netlist,” which is a record of all of the nets, or interconnections, between the cell pins. A layout typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The result is a set of design files known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator. During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The process of converting the specifications of an electrical circuit into a layout is called the physical design.
Cell placement in semiconductor fabrication involves a determination of where particular cells should optimally (or near-optimally) be located on the surface of a integrated circuit device. Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use computer-aided design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. Several different programming languages have been created for electronic design automation (EDA), including Verilog, VHDL and TDML. A typical EDA system receives one or more high level behavioral descriptions of an IC device, and translates this high level design language description into netlists of various levels of abstraction.
Faster performance and predictability of responses are elements of interest in circuit designs. As process technology scales to the deep-submicron (DSM) regime, clock-related problems such as clock skew and worst-case execution time are becoming increasingly important to the performance and reliability of IC chips and systems. With synchronous logic, static timing is performed to ensure that when a latch transitions, the correct value will meet the timing requirements of any downstream latch. One clock cycle is enough time for the transitioning value to be seen on the latch input without violating the setup requirements for that latch. Unfortunately, when a gating term in the clock logic is driven from an asynchronous source relative to a receiving latch, it becomes much more difficult to accurately test a circuit because the receive latch may be clocked at any time after the send latch transitions. The transitioning data may not have had enough time to reach the input of the receive latch, and if the new value of the send latch fails to reach the receive latch prior to its sampling of the input, the prior value will the latched. If the transition occurs within the setup and hold times required by the receive latch, the latch may become metastable. For a receive clock period, an old (pre-transition) value or new (post-transition) value may be latched, or the latch may become metastable.
It is commonplace for logic to be tested using a higher-level model than that which will be synthesized, e.g., the higher-level model may be a behavioral netlist and the post-synthesis model may be a gate-level netlist. In particular, logic written using a clock-gated implementation for sequential elements may sometimes be synthesized using a free-running, data-gated implementation. One example of such an implementation is illustrated in FIGS. 1A and 1B. FIG. 1A shows a typical netlist abstraction for a latch 2 having an enable line and a data input. The enable line is the output of an AND gate 4 whose inputs are the clock signal and a gating or control signal. This circuit construction is verified by the EDA tools, but the actual (physical) implementation is often different as depicted in FIG. 1B. The actual latch 2′ receives the clock signal directly at the enable line, while the data input is connected to a multiplexer 6 whose select line is connected to the control signal. The other input of multiplexer 6 is a feedback line from the output of latch 2′. The differences in the implementations arise from difficulties in breaking out the gating logic from the clock network. A problem which exists in this methodology is that certain asynchronous problems are undetectable in the behavioral model which may be apparent in the gate-level model. The testing performed on the high level model is thus inadequate for the netlist which will be synthesized.
There are many ways that a high-level behavioral model may be different from a gate-level model. There are also many ways in which latch ports may be modeled in both forms of netlist. However, when a behavioral model netlist is using a form for a clock-gated implementation and the post-synthesis netlist is using a free-running, data-gated implementation for their respective sequential elements, the post-synthesis netlist will always have a potential source of asynchronous problems. It would, therefore, be desirable to devise an improved method of modeling logic which could take into consideration possible differences between a higher-level model and a post-synthesis model. It would be further advantageous if the method could allow for earlier detection of asynchronous problems in gate-level models.